Test Failure: Transforms/LoopVectorize/ARM/mve-icmpcost.ll

Test source: git

Log:


stderr:

/home/nlopes/alive2/build/opt-alive.sh -passes=loop-vectorize -debug-only=loop-vectorize -disable-output < /bitbucket/nlopes/llvm/llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll 2>&1 | /bitbucket/nlopes/llvm/build/bin/FileCheck /bitbucket/nlopes/llvm/llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll # RUN: at line 1
+ /home/nlopes/alive2/build/opt-alive.sh -passes=loop-vectorize -debug-only=loop-vectorize -disable-output
+ /bitbucket/nlopes/llvm/build/bin/FileCheck /bitbucket/nlopes/llvm/llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
/bitbucket/nlopes/llvm/llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll:295:10: error: CHECK: expected string not found in input
; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction: %cmp1 = fcmp
         ^
<stdin>:1136:22: note: scanning from here
LV: Selecting VF: 16.
                     ^
<stdin>:1153:1: note: possible intended match here
LV: Found a vectorizable loop (16) in <stdin>
^

Input file: <stdin>
Check file: /bitbucket/nlopes/llvm/llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
             .
             .
             .
          1131: Cost of 0 for VF 16: induction instruction %incdec.ptr5 = getelementptr inbounds i8, ptr %pDst.addr.010, i32 1 
          1132: Cost of 0 for VF 16: induction instruction %pDst.addr.010 = phi ptr [ %incdec.ptr5, %while.body ], [ %pDst, %while.body.preheader ] 
          1133: Cost of 0 for VF 16: induction instruction %incdec.ptr2 = getelementptr inbounds i8, ptr %pSrcB.addr.09, i32 1 
          1134: Cost of 0 for VF 16: induction instruction %pSrcB.addr.09 = phi ptr [ %incdec.ptr2, %while.body ], [ %pSrcB, %while.body.preheader ] 
          1135: Cost of 1 for VF 16: exit condition instruction %cmp.not = icmp eq i32 %dec, 0 
          1136: LV: Selecting VF: 16. 
check:295'0                          X error: no match found
          1137: LV: The target has 13 registers of Generic::ScalarRC register class 
check:295'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          1138: LV: The target has 8 registers of Generic::VectorRC register class 
check:295'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          1139: LV: Loop does not require scalar epilogue 
check:295'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          1140: LV: Loop cost is 50 
check:295'0     ~~~~~~~~~~~~~~~~~~~~
          1141: LV: IC is 1 
check:295'0     ~~~~~~~~~~~~
             .
             .
             .
          1148:  1 for %diff.check4 = icmp ult i32 %1, 16 
check:295'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          1149:  1 for %conflict.rdx = or i1 %diff.check, %diff.check4 
check:295'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          1150: Total cost of runtime checks: 5 
check:295'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          1151: LV: Minimum required TC for runtime checks to be profitable:16 
check:295'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          1152: LV: Interleaving is not beneficial. 
check:295'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          1153: LV: Found a vectorizable loop (16) in <stdin> 
check:295'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
check:295'1     ?                                              possible intended match
          1154: LEV: Epilogue vectorization is not profitable for this loop 
check:295'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          1155: LV: Loop does not require scalar epilogue 
check:295'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          1156: LV: Loop does not require scalar epilogue 
check:295'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          1157: Executing best plan with VF=16, UF=1 
check:295'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
          1158: VPlan 'Final VPlan for VF={2,4,8,16},UF={1}' { 
check:295'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
             .
             .
             .
>>>>>>

 

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