Test Failure: Transforms/InstCombine/exact.ll

Test source: git

Log:

Source: <stdin>

----------------------------------------
define i32 @sdiv1(i32 %x) {
%0:
  %y = sdiv i32 %x, 8
  ret i32 %y
}
=>
define i32 @sdiv1(i32 %x) {
%0:
  %y = sdiv i32 %x, 8
  ret i32 %y
}
Transformation seems to be correct!


----------------------------------------
define i32 @sdiv2(i32 %x) {
%0:
  %y = sdiv exact i32 %x, 8
  ret i32 %y
}
=>
define i32 @sdiv2(i32 %x) {
%0:
  %y = ashr exact i32 %x, 3
  ret i32 %y
}
Transformation seems to be correct!


----------------------------------------
define <2 x i32> @sdiv2_vec(<2 x i32> %x) {
%0:
  %y = sdiv exact <2 x i32> %x, { 128, 128 }
  ret <2 x i32> %y
}
=>
define <2 x i32> @sdiv2_vec(<2 x i32> %x) {
%0:
  %y = ashr exact <2 x i32> %x, { 7, 7 }
  ret <2 x i32> %y
}
Transformation doesn't verify!
ERROR: Timeout


----------------------------------------
define i32 @sdiv3(i32 %x) {
%0:
  %y = sdiv i32 %x, 3
  %z = mul i32 %y, 3
  ret i32 %z
}
=>
define i32 @sdiv3(i32 %x) {
%0:
  %1 = srem i32 %x, 3
  %z = sub i32 %x, %1
  ret i32 %z
}
Transformation doesn't verify!
ERROR: Value mismatch

Example:
i32 %x = undef

Source:
i32 %y = #x00000000 (0)	[based on undef value]
i32 %z = #x00000000 (0)

Target:
i32 %1 = #x00000000 (0)
i32 %z = #x20000000 (536870912)
Source value: #x00000000 (0)
Target value: #x20000000 (536870912)


------------------- SMT STATS -------------------
Num queries: 15
Num invalid: 0
Num skips:   0
Num trivial: 12 (44.4%)
Num timeout: 1 (6.7%)
Num errors:  0 (0.0%)
Num SAT:     6 (40.0%)
Num UNSAT:   8 (53.3%)

stderr:

+ : 'RUN: at line 2'
+ /home/nlopes/alive2/build/opt-alive.sh -instcombine -S
+ /home/nlopes/llvm/build/bin/FileCheck /home/nlopes/llvm/llvm/test/Transforms/InstCombine/exact.ll

Alive2: Transform doesn't verify; aborting!
FileCheck error: '<stdin>' is empty.
FileCheck command line:  /home/nlopes/llvm/build/bin/FileCheck /home/nlopes/llvm/llvm/test/Transforms/InstCombine/exact.ll

NOTE: This test would pass if undef didn't exist!

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