Test source: git
Source: <stdin> ERROR: Unsupported instruction: %v = load volatile i32, i32* %p, align 4 ERROR: Unsupported instruction: %v = load volatile i32, i32* %p, align 4 ERROR: Unsupported instruction: %v = load volatile i32, i32* %p, align 4 ERROR: Unsupported instruction: %v = load volatile i32, i32* %p, align 4 ERROR: Unsupported instruction: %v = load volatile i32, i32* %p, align 4 ---------------------------------------- define i64 @rem_signed(i64 %x1, i64 %y2) { %0: %r = sdiv i64 %x1, %y2 %r7 = mul i64 %r, %y2 %r8 = sub i64 %x1, %r7 ret i64 %r8 } => define i64 @rem_signed(i64 %x1, i64 %y2) { %0: %x1.fr = freeze i64 %x1 %1 = srem i64 %x1.fr, %y2 ret i64 %1 } Transformation doesn't verify! ERROR: Timeout ---------------------------------------- define <4 x i32> @rem_signed_vec(<4 x i32> %t, <4 x i32> %u) { %0: %k = sdiv <4 x i32> %t, %u %l = mul <4 x i32> %k, %u %m = sub <4 x i32> %t, %l ret <4 x i32> %m } => define <4 x i32> @rem_signed_vec(<4 x i32> %t, <4 x i32> %u) { %0: %t.fr = freeze <4 x i32> %t %1 = srem <4 x i32> %t.fr, %u ret <4 x i32> %1 } Transformation doesn't verify! ERROR: Timeout ---------------------------------------- define i64 @rem_unsigned(i64 %x1, i64 %y2) { %0: %r = udiv i64 %x1, %y2 %r7 = mul i64 %r, %y2 %r8 = sub i64 %x1, %r7 ret i64 %r8 } => define i64 @rem_unsigned(i64 %x1, i64 %y2) { %0: %x1.fr = freeze i64 %x1 %1 = urem i64 %x1.fr, %y2 ret i64 %1 } Transformation doesn't verify! ERROR: Timeout ---------------------------------------- define i8 @big_divisor(i8 %x) { %0: %rem = urem i8 %x, 129 ret i8 %rem } => define i8 @big_divisor(i8 %x) { %0: %x.fr = freeze i8 %x %1 = icmp ult i8 %x.fr, 129 %2 = add i8 %x.fr, 127 %rem = select i1 %1, i8 %x.fr, i8 %2 ret i8 %rem } Transformation seems to be correct! ---------------------------------------- define i5 @biggest_divisor(i5 %x) { %0: %rem = urem i5 %x, 31 ret i5 %rem } => define i5 @biggest_divisor(i5 %x) { %0: %x.fr = freeze i5 %x %.not = icmp eq i5 %x.fr, 31 %rem = select i1 %.not, i5 0, i5 %x.fr ret i5 %rem } Transformation seems to be correct! ---------------------------------------- define i8 @urem_with_sext_bool_divisor(i1 %x, i8 %y) { %0: %s = sext i1 %x to i8 %rem = urem i8 %y, %s ret i8 %rem } => define i8 @urem_with_sext_bool_divisor(i1 %x, i8 %y) { %0: %1 = icmp eq i8 %y, 255 %rem = select i1 %1, i8 0, i8 %y ret i8 %rem } Transformation doesn't verify! ERROR: Value mismatch Example: i1 %x = #x1 (1) i8 %y = undef Source: i8 %s = #xff (255, -1) i8 %rem = #x00 (0) [based on undef value] Target: i1 %1 = #x0 (0) i8 %rem = #xff (255, -1) Source value: #x00 (0) Target value: #xff (255, -1) ------------------- SMT STATS ------------------- Num queries: 31 Num invalid: 0 Num skips: 0 Num trivial: 26 (45.6%) Num timeout: 3 (9.7%) Num errors: 0 (0.0%) Num SAT: 19 (61.3%) Num UNSAT: 9 (29.0%) Alive2: Transform doesn't verify; aborting!
+ : 'RUN: at line 2' + /home/nlopes/alive2/build/opt-alive.sh -passes=instcombine -S + /home/nlopes/llvm/build/bin/FileCheck /home/nlopes/llvm/llvm/test/Transforms/InstCombine/rem.ll FileCheck error: '<stdin>' is empty. FileCheck command line: /home/nlopes/llvm/build/bin/FileCheck /home/nlopes/llvm/llvm/test/Transforms/InstCombine/rem.ll
NOTE: This test would pass if undef didn't exist!