Test source: git
Source: <stdin> ---------------------------------------- define void @test1(i64 %trip, i1 %cond) { %entry: br label %loop_header %loop_header: %iv = phi i64 [ 0, %entry ], [ %iv_next, %loop_latch ] br i1 %cond, label %loop_latch, label %loop_exiting_bb1 %loop_exiting_bb1: br i1 0, label %loop_exiting_bb2, label %exit1 %loop_exiting_bb2: br i1 0, label %loop_latch, label %exit3 %loop_latch: %iv_next = add i64 %iv, 1 %cmp = icmp ne i64 %iv_next, %trip br i1 %cmp, label %loop_header, label %exit2.loopexit %exit2.loopexit: ret void %exit3: ret void %exit1: ret void } => define void @test1(i64 %trip, i1 %cond) { %entry: %0 = add i64 %trip, -1 %xtraiter = and i64 %trip, 7 %1 = icmp ult i64 %0, 7 br i1 %1, label %exit2.loopexit.unr-lcssa, label %entry.new %entry.new: %unroll_iter = sub i64 %trip, %xtraiter br label %loop_header %loop_header: %iv = phi i64 [ 0, %entry.new ], [ %iv_next.7, %loop_latch.7 ] %niter = phi i64 [ %unroll_iter, %entry.new ], [ %niter.nsub.7, %loop_latch.7 ] br i1 %cond, label %loop_latch, label %loop_exiting_bb1 %loop_exiting_bb1: br i1 0, label %loop_exiting_bb2, label %exit1.loopexit %loop_exiting_bb2: br i1 0, label %loop_latch, label %exit3.loopexit %loop_latch: %iv_next = add nsw nuw i64 %iv, 1 %niter.nsub = sub i64 %niter, 1 br i1 %cond, label %loop_latch.1, label %loop_exiting_bb1.1 %loop_exiting_bb1.1: br i1 0, label %loop_exiting_bb2.1, label %exit1.loopexit %loop_exiting_bb2.1: br i1 0, label %loop_latch.1, label %exit3.loopexit %loop_latch.1: %iv_next.1 = add nsw nuw i64 %iv_next, 1 %niter.nsub.1 = sub i64 %niter.nsub, 1 br i1 %cond, label %loop_latch.2, label %loop_exiting_bb1.2 %loop_exiting_bb1.2: br i1 0, label %loop_exiting_bb2.2, label %exit1.loopexit %loop_exiting_bb2.2: br i1 0, label %loop_latch.2, label %exit3.loopexit %loop_latch.2: %iv_next.2 = add nsw nuw i64 %iv_next.1, 1 %niter.nsub.2 = sub i64 %niter.nsub.1, 1 br i1 %cond, label %loop_latch.3, label %loop_exiting_bb1.3 %loop_exiting_bb1.3: br i1 0, label %loop_exiting_bb2.3, label %exit1.loopexit %loop_exiting_bb2.3: br i1 0, label %loop_latch.3, label %exit3.loopexit %loop_latch.3: %iv_next.3 = add nsw nuw i64 %iv_next.2, 1 %niter.nsub.3 = sub i64 %niter.nsub.2, 1 br i1 %cond, label %loop_latch.4, label %loop_exiting_bb1.4 %loop_exiting_bb1.4: br i1 0, label %loop_exiting_bb2.4, label %exit1.loopexit %loop_exiting_bb2.4: br i1 0, label %loop_latch.4, label %exit3.loopexit %loop_latch.4: %iv_next.4 = add nsw nuw i64 %iv_next.3, 1 %niter.nsub.4 = sub i64 %niter.nsub.3, 1 br i1 %cond, label %loop_latch.5, label %loop_exiting_bb1.5 %loop_exiting_bb1.5: br i1 0, label %loop_exiting_bb2.5, label %exit1.loopexit %loop_exiting_bb2.5: br i1 0, label %loop_latch.5, label %exit3.loopexit %loop_latch.5: %iv_next.5 = add nsw nuw i64 %iv_next.4, 1 %niter.nsub.5 = sub i64 %niter.nsub.4, 1 br i1 %cond, label %loop_latch.6, label %loop_exiting_bb1.6 %loop_exiting_bb1.6: br i1 0, label %loop_exiting_bb2.6, label %exit1.loopexit %loop_exiting_bb2.6: br i1 0, label %loop_latch.6, label %exit3.loopexit %loop_latch.6: %iv_next.6 = add nsw nuw i64 %iv_next.5, 1 %niter.nsub.6 = sub i64 %niter.nsub.5, 1 br i1 %cond, label %loop_latch.7, label %loop_exiting_bb1.7 %loop_exiting_bb1.7: br i1 0, label %loop_exiting_bb2.7, label %exit1.loopexit %loop_exiting_bb2.7: br i1 0, label %loop_latch.7, label %exit3.loopexit %loop_latch.7: %iv_next.7 = add i64 %iv_next.6, 1 %niter.nsub.7 = sub i64 %niter.nsub.6, 1 %niter.ncmp.7 = icmp ne i64 %niter.nsub.7, 0 br i1 %niter.ncmp.7, label %loop_header, label %exit2.loopexit.unr-lcssa.loopexit %exit2.loopexit.unr-lcssa.loopexit: %iv.unr.ph = phi i64 [ %iv_next.7, %loop_latch.7 ] br label %exit2.loopexit.unr-lcssa %exit3.loopexit: br label %exit3 %exit1.loopexit: br label %exit1 %exit2.loopexit.unr-lcssa: %iv.unr = phi i64 [ 0, %entry ], [ %iv.unr.ph, %exit2.loopexit.unr-lcssa.loopexit ] %lcmp.mod = icmp ne i64 %xtraiter, 0 br i1 %lcmp.mod, label %loop_header.epil.preheader, label %exit2.loopexit %loop_header.epil.preheader: br label %loop_header.epil %loop_header.epil: %iv.epil = phi i64 [ %iv.unr, %loop_header.epil.preheader ], [ %iv_next.epil, %loop_latch.epil ] %epil.iter = phi i64 [ %xtraiter, %loop_header.epil.preheader ], [ %epil.iter.sub, %loop_latch.epil ] br i1 %cond, label %loop_latch.epil, label %loop_exiting_bb1.epil %loop_exiting_bb1.epil: br i1 0, label %loop_exiting_bb2.epil, label %exit1.loopexit1 %loop_exiting_bb2.epil: br i1 0, label %loop_latch.epil, label %exit3.loopexit2 %loop_latch.epil: %iv_next.epil = add i64 %iv.epil, 1 %cmp.epil = icmp ne i64 %iv_next.epil, %trip %epil.iter.sub = sub i64 %epil.iter, 1 %epil.iter.cmp = icmp ne i64 %epil.iter.sub, 0 br i1 %epil.iter.cmp, label %loop_header.epil, label %exit2.loopexit.epilog-lcssa %exit2.loopexit.epilog-lcssa: br label %exit2.loopexit %exit3.loopexit2: br label %exit3 %exit3: ret void %exit1.loopexit1: br label %exit1 %exit1: ret void %exit2.loopexit: ret void } Transformation doesn't verify! ERROR: Source is more defined than target Example: i64 %trip = poison i1 %cond = #x0 (0) Source: i64 %iv = #x0000000000000000 (0) i64 %iv_next = #x0000000000000001 (1) i1 %cmp = poison Target: i64 %0 = poison i64 %xtraiter = poison i1 %1 = poison i64 %unroll_iter = poison i64 %iv = #x0000000000000000 (0) i64 %niter = poison i64 %iv_next = #x0000000000000001 (1) i64 %niter.nsub = poison i64 %iv_next.1 = #x0000000000000002 (2) i64 %niter.nsub.1 = poison i64 %iv_next.2 = #x0000000000000003 (3) i64 %niter.nsub.2 = poison i64 %iv_next.3 = #x0000000000000004 (4) i64 %niter.nsub.3 = poison i64 %iv_next.4 = #x0000000000000005 (5) i64 %niter.nsub.4 = poison i64 %iv_next.5 = #x0000000000000006 (6) i64 %niter.nsub.5 = poison i64 %iv_next.6 = #x0000000000000007 (7) i64 %niter.nsub.6 = poison i64 %iv_next.7 = #x0000000000000008 (8) i64 %niter.nsub.7 = poison i1 %niter.ncmp.7 = poison i64 %iv.unr.ph = #x0000000000000008 (8) i64 %iv.unr = #x0000000000000000 (0) i1 %lcmp.mod = poison i64 %iv.epil = #x0000000000000000 (0) i64 %epil.iter = #x0000000000000000 (0) i64 %iv_next.epil = #x0000000000000001 (1) i1 %cmp.epil = #x1 (1) i64 %epil.iter.sub = #xffffffffffffffff (18446744073709551615, -1) i1 %epil.iter.cmp = #x1 (1) ------------------- SMT STATS ------------------- Num queries: 2 Num invalid: 0 Num skips: 0 Num trivial: 20 (90.9%) Num timeout: 0 (0.0%) Num errors: 0 (0.0%) Num SAT: 2 (100.0%) Num UNSAT: 0 (0.0%) Alive2: Transform doesn't verify; aborting!
+ : 'RUN: at line 1' + /home/nlopes/alive2/build/opt-alive.sh -loop-unroll -unroll-runtime=true -unroll-runtime-epilog=true -unroll-runtime-multi-exit=true -verify-loop-lcssa -verify-dom-info -verify-loop-info -S + /home/nlopes/llvm/build/bin/FileCheck /home/nlopes/llvm/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll -check-prefix=EPILOG-NO-IC FileCheck error: '<stdin>' is empty. FileCheck command line: /home/nlopes/llvm/build/bin/FileCheck /home/nlopes/llvm/llvm/test/Transforms/LoopUnroll/runtime-loop-multiple-exits.ll -check-prefix=EPILOG-NO-IC