Test source: git
Source: <stdin>
-- 1. ModuleToFunctionPassAdaptor
-- 1. PassManager<Function> : Skipping NOP
-- 2. LoopVectorizePass
----------------------------------------
define void @arm_abs_q7(ptr nocapture nowrite %pSrc, ptr nocapture %pDst, i32 %blockSize) {
%entry:
%cmp.not19 = icmp eq i32 %blockSize, 0
br i1 %cmp.not19, label %while.end, label %while.body.preheader
%while.body.preheader:
br label %while.body
%while.body:
%pSrc.addr.022 = phi ptr [ %incdec.ptr, %while.body ], [ nocapture nowrite %pSrc, %while.body.preheader ]
%blkCnt.021 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.preheader ]
%pDst.addr.020 = phi ptr [ %incdec.ptr13, %while.body ], [ nocapture %pDst, %while.body.preheader ]
%incdec.ptr = gep inbounds ptr %pSrc.addr.022, 1 x i32 1
%0 = load i8, ptr %pSrc.addr.022, align 1
%cmp1 = icmp sgt i8 %0, 0
%cmp5 = icmp eq i8 %0, 128
%sub = sub i8 0, %0
%cond = select i1 %cmp5, i8 127, i8 %sub
%cond11 = select i1 %cmp1, i8 %0, i8 %cond
%incdec.ptr13 = gep inbounds ptr %pDst.addr.020, 1 x i32 1
store i8 %cond11, ptr %pDst.addr.020, align 1
%dec = add i32 %blkCnt.021, 4294967295
%cmp.not = icmp eq i32 %dec, 0
br i1 %cmp.not, label %while.end.loopexit, label %while.body
%while.end.loopexit:
br label %while.end
%while.end:
ret void
}
Transformation seems to be correct! (syntactically equal)
-- 3. LoopVectorizePass
----------------------------------------
define void @arm_abs_q7(ptr nocapture nowrite %pSrc, ptr nocapture %pDst, i32 %blockSize) {
%entry:
%cmp.not19 = icmp eq i32 %blockSize, 0
br i1 %cmp.not19, label %while.end, label %while.body.preheader
%while.body.preheader:
br label %while.body
%while.body:
%pSrc.addr.022 = phi ptr [ %incdec.ptr, %while.body ], [ nocapture nowrite %pSrc, %while.body.preheader ]
%blkCnt.021 = phi i32 [ %dec, %while.body ], [ %blockSize, %while.body.preheader ]
%pDst.addr.020 = phi ptr [ %incdec.ptr13, %while.body ], [ nocapture %pDst, %while.body.preheader ]
%incdec.ptr = gep inbounds ptr %pSrc.addr.022, 1 x i32 1
%0 = load i8, ptr %pSrc.addr.022, align 1
%cmp1 = icmp sgt i8 %0, 0
%cmp5 = icmp eq i8 %0, 128
%sub = sub i8 0, %0
%cond = select i1 %cmp5, i8 127, i8 %sub
%cond11 = select i1 %cmp1, i8 %0, i8 %cond
%incdec.ptr13 = gep inbounds ptr %pDst.addr.020, 1 x i32 1
store i8 %cond11, ptr %pDst.addr.020, align 1
%dec = add i32 %blkCnt.021, 4294967295
%cmp.not = icmp eq i32 %dec, 0
br i1 %cmp.not, label %while.end.loopexit, label %while.body
%while.end.loopexit:
br label %while.end
%while.end:
ret void
}
=>
define void @arm_abs_q7(ptr nocapture nowrite %pSrc, ptr nocapture %pDst, i32 %blockSize) {
%entry:
%pSrc2 = ptrtoint ptr nocapture nowrite %pSrc to i32
%pDst1 = ptrtoint ptr nocapture %pDst to i32
%cmp.not19 = icmp eq i32 %blockSize, 0
br i1 %cmp.not19, label %while.end, label %while.body.preheader
%while.body.preheader:
%min.iters.check = icmp ult i32 %blockSize, 16
br i1 %min.iters.check, label %scalar.ph, label %vector.memcheck
%vector.memcheck:
%0 = sub i32 %pDst1, %pSrc2
%diff.check = icmp ult i32 %0, 16
br i1 %diff.check, label %scalar.ph, label %vector.ph
%vector.ph:
%n.mod.vf = urem i32 %blockSize, 16
%n.vec = sub i32 %blockSize, %n.mod.vf
%ind.end = gep ptr nocapture nowrite %pSrc, 1 x i32 %n.vec
%ind.end3 = sub i32 %blockSize, %n.vec
%ind.end5 = gep ptr nocapture %pDst, 1 x i32 %n.vec
br label %vector.body
%vector.body:
%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
%1 = add i32 %index, 0
%next.gep = gep ptr nocapture nowrite %pSrc, 1 x i32 %1
%2 = add i32 %index, 0
%next.gep7 = gep ptr nocapture %pDst, 1 x i32 %2
%3 = gep ptr %next.gep, 1 x i32 0
%wide.load = load <16 x i8>, ptr %3, align 1
%4 = icmp sgt <16 x i8> %wide.load, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
%5 = icmp eq <16 x i8> %wide.load, { 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128 }
%6 = sub <16 x i8> { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, %wide.load
%7 = select <16 x i1> %5, <16 x i8> { 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127, 127 }, <16 x i8> %6
%8 = select <16 x i1> %4, <16 x i8> %wide.load, <16 x i8> %7
%9 = gep ptr %next.gep7, 1 x i32 0
store <16 x i8> %8, ptr %9, align 1
%index.next = add nuw i32 %index, 16
%10 = icmp eq i32 %index.next, %n.vec
br i1 %10, label %middle.block, label %vector.body
%middle.block:
%cmp.n = icmp eq i32 %blockSize, %n.vec
br i1 %cmp.n, label %while.end.loopexit, label %scalar.ph
%scalar.ph:
%bc.resume.val = phi ptr [ %ind.end, %middle.block ], [ nocapture nowrite %pSrc, %while.body.preheader ], [ nocapture nowrite %pSrc, %vector.memcheck ]
%bc.resume.val4 = phi i32 [ %ind.end3, %middle.block ], [ %blockSize, %while.body.preheader ], [ %blockSize, %vector.memcheck ]
%bc.resume.val6 = phi ptr [ %ind.end5, %middle.block ], [ nocapture %pDst, %while.body.preheader ], [ nocapture %pDst, %vector.memcheck ]
br label %while.body
%while.body:
%pSrc.addr.022 = phi ptr [ %incdec.ptr, %while.body ], [ %bc.resume.val, %scalar.ph ]
%blkCnt.021 = phi i32 [ %dec, %while.body ], [ %bc.resume.val4, %scalar.ph ]
%pDst.addr.020 = phi ptr [ %incdec.ptr13, %while.body ], [ %bc.resume.val6, %scalar.ph ]
%incdec.ptr = gep inbounds ptr %pSrc.addr.022, 1 x i32 1
%11 = load i8, ptr %pSrc.addr.022, align 1
%cmp1 = icmp sgt i8 %11, 0
%cmp5 = icmp eq i8 %11, 128
%sub = sub i8 0, %11
%cond = select i1 %cmp5, i8 127, i8 %sub
%cond11 = select i1 %cmp1, i8 %11, i8 %cond
%incdec.ptr13 = gep inbounds ptr %pDst.addr.020, 1 x i32 1
store i8 %cond11, ptr %pDst.addr.020, align 1
%dec = add i32 %blkCnt.021, 4294967295
%cmp.not = icmp eq i32 %dec, 0
br i1 %cmp.not, label %while.end.loopexit, label %while.body
%while.end.loopexit:
br label %while.end
%while.end:
ret void
}
Transformation doesn't verify! (unsound)
ERROR: Source is more defined than target
Example:
ptr nocapture nowrite %pSrc = null
ptr nocapture %pDst = null
i32 %blockSize = #x00000000 (0)
Source:
i1 %cmp.not19 = #x1 (1)
>> Jump to %while.end
SOURCE MEMORY STATE
===================
NON-LOCAL BLOCKS:
Block 0 > size: 0 align: 1 alloc type: 0 address: 0
Block 1 > size: 0 align: 1 alloc type: 0 address: 1
Block 2 > size: 0 align: 2147483648 alloc type: 0 address: 2147483648
Target:
i32 %pSrc2 = UB triggered!
Pass: LoopVectorizePass
Command line: '/home/nlopes/llvm/build/bin/opt' '-load=/home/nlopes/alive2/build/tv/tv.so' '-load-pass-plugin=/home/nlopes/alive2/build/tv/tv.so' '-tv-exit-on-error' '-passes=loop-vectorize,instcombine,simplifycfg' '-simplifycfg-require-and-preserve-domtree=1' '-S' '-o' '-' '-tv-smt-to=20000' '-tv-report-dir=/home/nlopes/alive2/build/logs' '-tv-smt-stats'
Wrote bitcode to: "/home/nlopes/alive2/build/logs/in_Th7RVbxg_XWT5.bc"
------------------- SMT STATS -------------------
Num queries: 23
Num invalid: 0
Num skips: 0
Num trivial: 4 (14.8%)
Num timeout: 0 (0.0%)
Num errors: 0 (0.0%)
Num SAT: 22 (95.7%)
Num UNSAT: 1 (4.3%)
Alive2: Transform doesn't verify; aborting!
+ : 'RUN: at line 2' + /home/nlopes/alive2/build/opt-alive.sh -passes=loop-vectorize,instcombine,simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S -o - + /bitbucket/nlopes/llvm/build/bin/FileCheck /bitbucket/nlopes/llvm/llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll FileCheck error: '<stdin>' is empty. FileCheck command line: /bitbucket/nlopes/llvm/build/bin/FileCheck /bitbucket/nlopes/llvm/llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll